PI(s): Aman Arora
UNIVERSITY: Arizona State University
CODE: 116.ASU.AROR.25.Y3
STATUS: Completed
Defense systems must integrate legacy electronics (often running at 3.3 V–5 V and older packages) with modern subsystems (≈1.2 V–2 V). Lack of flexible, trusted, U.S.-fabricated devices that can programmatically bridge these voltage domains drives cost, schedule risk, and obsolescence pain across DoD programs.
Motivation: A reconfigurable, secure, and domestically fabricated solution aligns with DMEA’s mission to “deliver microelectronics solutions to meet DoD needs” and addresses a defense electronics obsolescence market projected at ~$2.5–$3B in 2025. Programmable voltage translation enables reuse across platforms, faster retrofits, and longer system life.
Objectives: Design a voltage‑translation FPGA with on‑chip, digitally controlled LDOs and level‑shifter‑integrated I/O blocks that route between high‑voltage (VH) and low‑voltage (VL) domains while supporting core logic (Vc). Target VH ≈ 5–2.5 V, VL ≈ 2–1.2 V (tunable per DMEA needs). Deliver an EDA toolchain (based on OpenFPGA) that generates the fabric, bitstream, timing collateral, and verification assets for the custom architecture.
