Project

DESCRIPTION:

In resource-constrained edge devices, executing applications locally is increasingly necessary, as transmitting data to centralized servers adds latency, energy overheads, and security risks. To mitigate these issues, edge platforms are evolving to support diverse workloads within ever more stringent power and area constraints. A key bottleneck is the rigid support for fixed number formats and precision in arithmetic units. This has led to the Transprecision Computing paradigm, which dynamically adjusts number format and precision to balance energy efficiency and accuracy, reducing energy consumption and improving performance. Recently, novel number representations such as bfloat16, minifloat, PXR24, and Posit—have emerged, offering better trade-offs between dynamic range, accuracy, and computational efficiency than IEEE-754 formats. However, support for these formats remains limited in most general-purpose ALUs in edge processors. The primary goal of this project is to develop innovative hardware architectures and algorithms that empower edge devices to meet SWAP (Size, Weight, Area, and Power) constraints while efficiently executing emerging compute-intensive applications. These applications involve diverse signal processing tasks—including audio, image, WiFi, Bluetooth, and 5G/6G—leveraging both traditional and advanced machine learning techniques. This goal will be achieved through the design and implementation of an ultra-low-power, compact Transprecision Arithmetic Logic Unit (TALU) for edge computing platforms. The TALU will feature: (1) multi-format support ensuring compatibility with IEEE-754 and emerging numerical representations; (2) dynamic selection of arithmetic precision to optimize energy efficiency while maintaining output fidelity; (3) scalar and vector operations to meet workload-specific accuracy demands; (4) area and power efficiency for battery-powered or low-power edge processors.